1. Technical Field
The present invention is generally directed to improved multichip integrated circuit modules and, in particular, to such structures designed to facilitate three-dimensional stacking of modules.
2. Description of the Prior Art
Three-dimensional structures are especially important in the multichip module field because they provide a method for continuing an improved performance level derived from a single multichip module. In particular, the performance level of a conventional system suffers as soon as a signal is connected from the multichip module to the next level of interconnect, for example, to a printed circuit board. There are many forms that reduction in performance level can take. These include: the number of input/outputs required; electrical speed; power delivery; volume and weight considerations; and power dissipation.
A present state of the art multichip module system consists of one or more multichip modules connected together by a printed circuit board To understand the difference in performance level in such a system, one need only consider typical line and space capabilities on the multichip module in comparison with the printed circuit board. Typically, line widths are 10 mils and spaces are 10-15 mils on a printed circuit board. The much larger interconnects on the printed circuit board necessarily result in higher capacitance and fewer lines in a given area. Higher line capacitance in turn reduces the speed capability of the system. Also, as noted, a fewer number of interconnects per unit area can be provided, which produces a square law effect rather than linear. A typical reduction in interconnect density can be as high as 100 to 1 in going from a multichip module to a printed circuit board. A somewhat more subtle effect is the discontinuity associated with the connection from the printed circuit board to the multichip module, especially when using conventional lead type packages. This discontinuity limits the ultimate performance of the digital system to a level below one GHz, regardless of the care taken in laying out the printed circuit board and/or the multichip module.
As a result of lower interconnect density, the size of the system is dramatically increased. Further, although the multichip module gives a considerable decrease in system size over a system where each individual chip is connected on a circuit board, the use of a circuit board to interconnect individual multichip modules still results in a substantial increase in weight and volume of the overall system, i.e., compared to the weight and volume of the multichip module itself. It should be noted that in certain applications, such as space borne and portable electrical equipment applications, there is a very significant need for reduction in the total weight and volume of the system assembly. In aircraft avionics the same is true, especially given the need in retrofit markets to redo existing electronics in a much smaller package so that additional electronic capability can be added to existing aircraft. In addition, decreases in volume of an electronic system can result in the same system capability in a desk top computer as existed in a previous desk top unit coupled to a side rack standing on the floor.
One possible prior art approach to maintaining multichip module performance in electronic systems is to increase the area of the multichip module. This approach, however, has some very significant limits. As the size of the system is increased, the overall yield decreases. Ultimately the system can no longer be produced cost effectively. In addition, as the area of the system is increased its electrical performance suffers. This is due to the fact that interconnect lines have a finite resistance and this resistance quickly approaches the characteristic impedance of the interconnect as the size of the module increases beyond 2 inches by 2 inches. Another fundamental physical limitation in a very high performance system is the propagation time for signals. In a typical dielectric of relative permitivity of three, a signal propagates only four centimeters in 0.3 nanosecond. As a result, at clock rates above one GHz all electrical components must be within five centimeters, which is simply insufficient to allow a complex system to be constructed. Three-dimensional techniques can increase the number of components within a five centimeter range by factors of 50 to 100 in the ultimate limit.
The basic problem in a stack of multichip modules is to provide the required number of interconnects between modules within a given space. Typical prior art methods for interconnecting modules in a stack have used interconnects at the periphery of the module. By way of example, the HDI approach (which is described in co-filed patent application entitled, "Multichip Integratd Circuit Module and Method of Fabrication," Ser. No. 07/676,937, the entirety of which is hereby incorporated herein by reference) stacks modules with wrap around connections on the edge of the modules. Subsequently, an overlay layer is provided which interconnects between modules by making contact to the wrap around conductors. This approach has two disadvantages. The number of contacts is limited to the wiring pitch which can be accommodated around the periphery of the module. A 10 mil pitch is a practical upper limit and would result in a 2 by 2 module with 200 connections per side being available. While this number is sufficient for many applications, it does not compare to the wiring density available internal to the module itself. In addition, interconnects between modules are forced to go to the periphery of the module and, therefore, the interconnect distance between adjacent circuitry in two modules is, on average, twice as long as the distance between adjacent circuitry on the same module.
Another technique for interconnecting modules is the so called button contact. The button contact has the advantage that it can be provided with a relatively fine pitch in an area array format. It provides a short interconnect with a reasonably high degree of reliability and the interconnect is temporary in nature so that modules in the stack can be removed or replaced. In prior art systems where buttons have been used to interconnect stacks of circuit boards, rows of button contacts are used to interconnect between pads on the periphery of the circuit boards. Pursuant to the present invention, an ideal interconnect in terms of providing the maximum number of interconnects between modules is an area array interconnect where the entire top and bottom surface area of the module are covered with interconnect pads. If, for example, button contacts on 20 mil centers were used, the total number of interconnects available in a 2 inch by 2 inch module would be 10,000 interconnects. This number is compatible with the number of interconnects in a 2 inch by 2 inch multichip module. The major factor in prior art module stacks that prevents fabricating a module with area arrays covering the entire top and bottom surface is that there must be space provided for the electronic components themselves. Contacts passed from the bottom of a circuit board cannot reach the top of that circuit board because they would have to pass directly through an electronic component. In addition, while contacts could be provided on the printed circuit board side, there is no commensurate area for interconnect arrays above the components. There are no known systems in which arrays of interconnect pads are provided on both the top and bottom side of a module which could allow interconnect between modules by button contacts, solder bumps or the like.
Another problem associated with interconnect between modules occurs in high speed systems. In these systems, there is a need to provide an impedance match which matches the characteristic impedance of the lines which are interconnected. If a good match is not provided, the discontinuity will cause reflections which can result in erroneous data transmission. In addition, it is necessary to reduce cross coupling between adjacent lines both within the module and in the interconnect which connects adjacent modules.
In some systems, mechanical interconnects such as button contacts are not allowed because the reliability of mechanical contacts is substantially less than the reliability of pure metallurgical interconnect. In these systems, the problem is to provide a metallurgical interconnect which has high input/output capability and which provides very short interconnect distance between adjacent interconnected modules.
Removal of heat is a problem compounded by the increased number of components in a small space, which results when stacking multichip modules. If a heat sink is used between each module, the problem is to provide an interconnect between those modules which couples around the heat sink. In systems where weight and volume or lead length are major considerations, the problem is to provide maximum heat flow from one module to the next so that a number of modules can be stacked together before attaching them to a heat sink. Printed circuit board modules are virtually incapable of providing heat flow through the module. This is because the circuit board itself and the top of the packaged component both provide effective thermal barriers to heat flow. In the HDI stacked module with interconnect on the periphery, a reasonable amount of heat flow through the module could be provided. The major insulating barrier occurs in the interconnect, on top of the chips, and in the material used to attach the modules together. In view of the above, the need continues to exist in the art for an improved multichip integrated circuit package and heat sink structure designed to facilitate three-dimensional stacking of multichip modules.